-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 8.1 Build 163 10/28/2008 SJ Web Edition"

-- DATE "03/16/2009 15:03:35"

-- 
-- Device: Altera EP2C35F672C6 Package FBGA672
-- 

-- 
-- This VHDL file should be used for Custom VHDL only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	FPGAtest IS
    PORT (
	clk : IN std_logic;
	input : IN std_logic_vector(3 DOWNTO 0);
	received_data : IN std_logic_vector(3 DOWNTO 0);
	key : IN std_logic;
	output : OUT std_logic_vector(3 DOWNTO 0);
	ledg : OUT std_logic_vector(3 DOWNTO 0);
	transmit_error : OUT std_logic;
	transmit_valid : OUT std_logic
	);
END FPGAtest;

ARCHITECTURE structure OF FPGAtest IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_input : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_received_data : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_key : std_logic;
SIGNAL ww_output : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_ledg : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_transmit_error : std_logic;
SIGNAL ww_transmit_valid : std_logic;
SIGNAL \mem|altsyncram_component|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(143 DOWNTO 0);
SIGNAL \mem|altsyncram_component|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(15 DOWNTO 0);
SIGNAL \mem|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\ : std_logic_vector(143 DOWNTO 0);
SIGNAL \clk~combout\ : std_logic;
SIGNAL \~GND~combout\ : std_logic;
SIGNAL \address_ram[0]~58_combout\ : std_logic;
SIGNAL \address_ram[0]~regout\ : std_logic;
SIGNAL \address_ram[1]~44_combout\ : std_logic;
SIGNAL \address_ram[1]~regout\ : std_logic;
SIGNAL \address_ram[1]~45\ : std_logic;
SIGNAL \address_ram[2]~46_combout\ : std_logic;
SIGNAL \address_ram[2]~regout\ : std_logic;
SIGNAL \address_ram[2]~47\ : std_logic;
SIGNAL \address_ram[3]~48_combout\ : std_logic;
SIGNAL \address_ram[3]~regout\ : std_logic;
SIGNAL \address_ram[3]~49\ : std_logic;
SIGNAL \address_ram[4]~50_combout\ : std_logic;
SIGNAL \address_ram[4]~regout\ : std_logic;
SIGNAL \address_ram[4]~51\ : std_logic;
SIGNAL \address_ram[5]~52_combout\ : std_logic;
SIGNAL \address_ram[5]~regout\ : std_logic;
SIGNAL \address_ram[5]~53\ : std_logic;
SIGNAL \address_ram[6]~54_combout\ : std_logic;
SIGNAL \address_ram[6]~regout\ : std_logic;
SIGNAL \address_ram[6]~55\ : std_logic;
SIGNAL \address_ram[7]~56_combout\ : std_logic;
SIGNAL \address_ram[7]~regout\ : std_logic;
SIGNAL \mem|altsyncram_component|auto_generated|q_a[0]\ : std_logic;
SIGNAL \mem|altsyncram_component|auto_generated|q_a[1]\ : std_logic;
SIGNAL \mem|altsyncram_component|auto_generated|q_a[2]\ : std_logic;
SIGNAL \mem|altsyncram_component|auto_generated|q_a[3]\ : std_logic;
SIGNAL \key~combout\ : std_logic;
SIGNAL \process_1~0_combout\ : std_logic;
SIGNAL \LessThan0~201_combout\ : std_logic;
SIGNAL \LessThan0~202_combout\ : std_logic;
SIGNAL \LessThan0~203_combout\ : std_logic;
SIGNAL \send_enable~regout\ : std_logic;
SIGNAL \ALT_INV_process_1~0_combout\ : std_logic;
SIGNAL \ALT_INV_clk~combout\ : std_logic;

BEGIN

ww_clk <= clk;
ww_input <= input;
ww_received_data <= received_data;
ww_key <= key;
output <= ww_output;
ledg <= ww_ledg;
transmit_error <= ww_transmit_error;
transmit_valid <= ww_transmit_valid;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\mem|altsyncram_component|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
& gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \~GND~combout\ & \~GND~combout\ & \~GND~combout\ & \~GND~combout\);

\mem|altsyncram_component|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \address_ram[7]~regout\ & \address_ram[6]~regout\ & \address_ram[5]~regout\ & \address_ram[4]~regout\ & \address_ram[3]~regout\ & 
\address_ram[2]~regout\ & \address_ram[1]~regout\ & \address_ram[0]~regout\);

\mem|altsyncram_component|auto_generated|q_a[0]\ <= \mem|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(0);
\mem|altsyncram_component|auto_generated|q_a[1]\ <= \mem|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(1);
\mem|altsyncram_component|auto_generated|q_a[2]\ <= \mem|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(2);
\mem|altsyncram_component|auto_generated|q_a[3]\ <= \mem|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\(3);
\ALT_INV_process_1~0_combout\ <= NOT \process_1~0_combout\;
\ALT_INV_clk~combout\ <= NOT \clk~combout\;

\clk~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\~GND\ : cycloneii_lcell_comb
-- Equation(s):
-- \~GND~combout\ = GND

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	combout => \~GND~combout\);

\address_ram[0]~58\ : cycloneii_lcell_comb
-- Equation(s):
-- \address_ram[0]~58_combout\ = !\address_ram[0]~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \address_ram[0]~regout\,
	combout => \address_ram[0]~58_combout\);

\address_ram[0]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datain => \address_ram[0]~58_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \address_ram[0]~regout\);

\address_ram[1]~44\ : cycloneii_lcell_comb
-- Equation(s):
-- \address_ram[1]~44_combout\ = \address_ram[1]~regout\ & (\address_ram[0]~regout\ $ VCC) # !\address_ram[1]~regout\ & \address_ram[0]~regout\ & VCC
-- \address_ram[1]~45\ = CARRY(\address_ram[1]~regout\ & \address_ram[0]~regout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110011010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \address_ram[1]~regout\,
	datab => \address_ram[0]~regout\,
	datad => VCC,
	combout => \address_ram[1]~44_combout\,
	cout => \address_ram[1]~45\);

\address_ram[1]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datain => \address_ram[1]~44_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \address_ram[1]~regout\);

\address_ram[2]~46\ : cycloneii_lcell_comb
-- Equation(s):
-- \address_ram[2]~46_combout\ = \address_ram[2]~regout\ & !\address_ram[1]~45\ # !\address_ram[2]~regout\ & (\address_ram[1]~45\ # GND)
-- \address_ram[2]~47\ = CARRY(!\address_ram[1]~45\ # !\address_ram[2]~regout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \address_ram[2]~regout\,
	datad => VCC,
	cin => \address_ram[1]~45\,
	combout => \address_ram[2]~46_combout\,
	cout => \address_ram[2]~47\);

\address_ram[2]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datain => \address_ram[2]~46_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \address_ram[2]~regout\);

\address_ram[3]~48\ : cycloneii_lcell_comb
-- Equation(s):
-- \address_ram[3]~48_combout\ = \address_ram[3]~regout\ & (\address_ram[2]~47\ $ GND) # !\address_ram[3]~regout\ & !\address_ram[2]~47\ & VCC
-- \address_ram[3]~49\ = CARRY(\address_ram[3]~regout\ & !\address_ram[2]~47\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \address_ram[3]~regout\,
	datad => VCC,
	cin => \address_ram[2]~47\,
	combout => \address_ram[3]~48_combout\,
	cout => \address_ram[3]~49\);

\address_ram[3]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datain => \address_ram[3]~48_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \address_ram[3]~regout\);

\address_ram[4]~50\ : cycloneii_lcell_comb
-- Equation(s):
-- \address_ram[4]~50_combout\ = \address_ram[4]~regout\ & !\address_ram[3]~49\ # !\address_ram[4]~regout\ & (\address_ram[3]~49\ # GND)
-- \address_ram[4]~51\ = CARRY(!\address_ram[3]~49\ # !\address_ram[4]~regout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \address_ram[4]~regout\,
	datad => VCC,
	cin => \address_ram[3]~49\,
	combout => \address_ram[4]~50_combout\,
	cout => \address_ram[4]~51\);

\address_ram[4]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datain => \address_ram[4]~50_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \address_ram[4]~regout\);

\address_ram[5]~52\ : cycloneii_lcell_comb
-- Equation(s):
-- \address_ram[5]~52_combout\ = \address_ram[5]~regout\ & (\address_ram[4]~51\ $ GND) # !\address_ram[5]~regout\ & !\address_ram[4]~51\ & VCC
-- \address_ram[5]~53\ = CARRY(\address_ram[5]~regout\ & !\address_ram[4]~51\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \address_ram[5]~regout\,
	datad => VCC,
	cin => \address_ram[4]~51\,
	combout => \address_ram[5]~52_combout\,
	cout => \address_ram[5]~53\);

\address_ram[5]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datain => \address_ram[5]~52_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \address_ram[5]~regout\);

\address_ram[6]~54\ : cycloneii_lcell_comb
-- Equation(s):
-- \address_ram[6]~54_combout\ = \address_ram[6]~regout\ & !\address_ram[5]~53\ # !\address_ram[6]~regout\ & (\address_ram[5]~53\ # GND)
-- \address_ram[6]~55\ = CARRY(!\address_ram[5]~53\ # !\address_ram[6]~regout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \address_ram[6]~regout\,
	datad => VCC,
	cin => \address_ram[5]~53\,
	combout => \address_ram[6]~54_combout\,
	cout => \address_ram[6]~55\);

\address_ram[6]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datain => \address_ram[6]~54_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \address_ram[6]~regout\);

\address_ram[7]~56\ : cycloneii_lcell_comb
-- Equation(s):
-- \address_ram[7]~56_combout\ = \address_ram[6]~55\ $ !\address_ram[7]~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000001111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => \address_ram[7]~regout\,
	cin => \address_ram[6]~55\,
	combout => \address_ram[7]~56_combout\);

\address_ram[7]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datain => \address_ram[7]~56_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \address_ram[7]~regout\);

\mem|altsyncram_component|auto_generated|ram_block1a0\ : cycloneii_ram_block
-- pragma translate_off
GENERIC MAP (
	mem_init0 => X"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000092514AF60000000000000000000000000000000000FFFFFFFB9B785634123107FEA93307FEA96FD80040004000002E0000450008522D8A681E00922D8A681E00D555555555555555",
	data_interleave_offset_in_bits => 1,
	data_interleave_width_in_bits => 1,
	init_file => "FPGAtest.mif",
	init_file_layout => "port_a",
	logical_ram_name => "ram:mem|altsyncram:altsyncram_component|altsyncram_79e1:auto_generated|ALTSYNCRAM",
	operation_mode => "single_port",
	port_a_address_clear => "none",
	port_a_address_width => 8,
	port_a_byte_enable_clear => "none",
	port_a_byte_enable_clock => "none",
	port_a_data_in_clear => "none",
	port_a_data_out_clear => "none",
	port_a_data_out_clock => "clock0",
	port_a_data_width => 4,
	port_a_first_address => 0,
	port_a_first_bit_number => 0,
	port_a_last_address => 255,
	port_a_logical_ram_depth => 144,
	port_a_logical_ram_width => 4,
	port_a_write_enable_clear => "none",
	port_b_address_width => 8,
	port_b_data_width => 4,
	ram_block_type => "M4K",
	safe_write => "err_on_2clk")
-- pragma translate_on
PORT MAP (
	portawe => GND,
	clk0 => \ALT_INV_clk~combout\,
	portadatain => \mem|altsyncram_component|auto_generated|ram_block1a0_PORTADATAIN_bus\,
	portaaddr => \mem|altsyncram_component|auto_generated|ram_block1a0_PORTAADDR_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	portadataout => \mem|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\);

\key~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_key,
	combout => \key~combout\);

\process_1~0\ : cycloneii_lcell_comb
-- Equation(s):
-- \process_1~0_combout\ = \key~combout\ & \clk~combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \key~combout\,
	datad => \clk~combout\,
	combout => \process_1~0_combout\);

\LessThan0~201\ : cycloneii_lcell_comb
-- Equation(s):
-- \LessThan0~201_combout\ = \address_ram[7]~regout\ & (\address_ram[5]~regout\ # \address_ram[6]~regout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \address_ram[5]~regout\,
	datac => \address_ram[6]~regout\,
	datad => \address_ram[7]~regout\,
	combout => \LessThan0~201_combout\);

\LessThan0~202\ : cycloneii_lcell_comb
-- Equation(s):
-- \LessThan0~202_combout\ = \address_ram[3]~regout\ # \address_ram[0]~regout\ # \address_ram[2]~regout\ # \address_ram[1]~regout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \address_ram[3]~regout\,
	datab => \address_ram[0]~regout\,
	datac => \address_ram[2]~regout\,
	datad => \address_ram[1]~regout\,
	combout => \LessThan0~202_combout\);

\LessThan0~203\ : cycloneii_lcell_comb
-- Equation(s):
-- \LessThan0~203_combout\ = !\LessThan0~201_combout\ & (!\address_ram[7]~regout\ # !\LessThan0~202_combout\ # !\address_ram[4]~regout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001001100110011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \address_ram[4]~regout\,
	datab => \LessThan0~201_combout\,
	datac => \LessThan0~202_combout\,
	datad => \address_ram[7]~regout\,
	combout => \LessThan0~203_combout\);

send_enable : cycloneii_lcell_ff
PORT MAP (
	clk => \ALT_INV_clk~combout\,
	datain => \LessThan0~203_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \send_enable~regout\);

\input[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_input(0));

\input[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_input(1));

\input[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_input(2));

\input[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_input(3));

\received_data[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_received_data(0));

\received_data[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_received_data(1));

\received_data[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_received_data(2));

\received_data[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_received_data(3));

\output[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \mem|altsyncram_component|auto_generated|q_a[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_output(0));

\output[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \mem|altsyncram_component|auto_generated|q_a[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_output(1));

\output[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \mem|altsyncram_component|auto_generated|q_a[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_output(2));

\output[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \mem|altsyncram_component|auto_generated|q_a[3]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_output(3));

\ledg[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_process_1~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ledg(0));

\ledg[1]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ledg(1));

\ledg[2]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ledg(2));

\ledg[3]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_ledg(3));

\transmit_error~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_transmit_error);

\transmit_valid~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "output",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => \send_enable~regout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_transmit_valid);
END structure;


